1. Field of the Invention
Embodiments of the invention relate generally to semiconductor devices. More particularly, the invention, in various embodiments, pertains to assemblies of stacked semiconductor dice, structures incorporated in such assemblies, methods of fabricating such assemblies and systems including such assemblies.
2. Discussion of Related Art
The use of integrated circuit (IC) chips or dice is widespread in electronics applications. Continuing progress in the manufacture of IC chips has resulted in chips of greatly increased density, i.e., a higher number of semiconductor die per footprint area of each chip. In order to produce increasingly complex electronic structures exhibiting high circuit densities, it has become common practice to stack dice on a lead frame die paddle to create what is known in the art as a multi-chip package or multi-chip module (MCM). One challenge posed by conventional stacked die MCM configurations is that of providing sufficient access to the bond pads of dice below the top die in a stack to enable wire bonding using conventional equipment. Current stacked die configurations for an MCM include a wedding cake, or pyramid, where the die size becomes progressively smaller from the bottom to the top of the stack, alternating large dice with small dice, using substantially the same size dice superimposed one upon another with laterally smaller spacers between the dice to allow access to the bond pads, using dice bonded back-to-back, and mounting one or more dice on opposite sides of a die paddle. Some of these variations of multi-chip packages are described in U.S. Pat. Nos. 6,514,794 and 6,376,904 each to Haba et al., U.S. Pat. No. 6,621,155 to Perino et al., U.S. Pat. No. 5,495,398 to Takiar et al. and U.S. Pat. No. 6,900,528 to Mess et al.
A shingle stack is an MCM configuration where a plurality of dice is stacked on a die paddle and wherein each die is partially offset from the next lower die in the stack in order to expose the bond pads of the next lower die. However, when the desired MCM configuration includes leads on opposite sides, such as in a thin small outline package (TSOP) or small outline J-lead package (SOJ) configuration and the semiconductor bond pads are only formed along a single side of the active surface of each die, a redistribution layer either formed on the active surface of the uppermost die or applied as a separate structure thereto is required to electrically communicate with the leads on the opposite sides of the package opposite the location of the semiconductor die bond pads.
While the die paddle provides alignment and support of the semiconductor die stack during assembly, the die paddle requires a significant amount of space or “real estate” and also adds significantly to the overall height of the die stack. Further, when such a semiconductor die assembly is in operation, temperature change can create significant thermal stress between the die paddle and the adjacent semiconductor die due to the significantly greater coefficient of thermal expansion (CTE) of the metal die paddle relative to the silicon material of the semiconductor dice, physically cracking the transfer-molded package structure encapsulating the stacked die assembly, compromising package integrity and potentially leading to device failure.
FIG. 1A depicts one embodiment of a known, although not prior art, semiconductor die assembly 10 in a shingle stack configuration wherein semiconductor dice 20A, 20B, 20C and 20D are mutually adhesively secured with segments of die attach film 12 and the lowermost die 20A to the die paddle 14 of a lead frame, with each successive die 20B to 20D partially offset from that immediately below it in order to expose the bond pads 22 of the underlying dice. It should be noted that die attach film 12 is depicted in FIGS. lA and 1B as merely the boundary between adjacent components due to the relatively thin nature thereof, for the sake of convenience. A redistribution element in the form of silicon interposer 50 bearing conductive traces is adhesively secured with another segment of die attach film 12 to the active surface of die 20D. Bond wires 30 are used for electrical communication as required between the dice 20A, 20B, 20C, 20D, the conductive traces of silicon interposer 50 and the conductive lead fingers 18 on both sides of the die stack for the semiconductor die assembly 10. The components of semiconductor die assembly 10 are sealed with an encapsulant structure 16, with only the outer ends of conductive lead fingers 18 exposed beyond encapsulant structure 16 to allow electrical connection of the semiconductor die assembly 10 with higher level packaging, such as a printed circuit board or other carrier structure.
In the embodiment of FIG. 1A, the lead frame die paddle 14 is of 127 μm thickness, semiconductor dice 20A through 20D are each of 90 μm thickness, silicon interposer 50 is of 100 μm thickness, and the segments of die attach film 12 are each of 10 μm thickness. Of course, the portions of encapsulant structure 16 above and below the die stack adds significantly to the package height.
FIG. 1B depicts another embodiment of a known, but not prior art, semiconductor die assembly 10′ in a shingle stack configuration wherein semiconductor dice 20A, 20B, 20C and 20D′ are mutually adhesively secured with segments of die attach film 12 and the lowermost die 20A to the die paddle 14, with each successive die 20B to 20D′ partially offset from that immediately below it in order to expose the bond pads 22 of the underlying dice. Unlike the embodiment of FIG. 1A, no separate redistribution element is employed; rather, uppermost semiconductor die 20D′ is provided with a redistribution layer comprising conductive traces extending over the active surface thereof Bond wires 30 are used for electrical communication as required between the dice 20A, 20B, 20C, 20D′, the conductive traces of the redistribution layer of uppermost semiconductor die 20D′, and the conductive lead fingers 18 on both sides of the die stack for the semiconductor die assembly 10′. The components of semiconductor die assembly 10′ are sealed with an encapsulant structure 16 with the outer ends of conductive lead fingers 18 exposed beyond encapsulant structure 16 to allow electrical connection of the semiconductor die assembly 10′ with higher level packaging such as a printed circuit board or other carrier structure.
In the embodiment of FIG. 1B, the lead frame die paddle 14 is of 130 μm thickness, semiconductor dice 20A through 20C are each of 100 μm thickness, semiconductor die 20D′, including a redistribution layer, is of 150 μm thickness, and the segments of die attach film 12 are each of 10 μm thickness. Again, encapsulant structure 16 above and below the die stack adds significantly to the package height.
Stacked, multi-die packages have become ever-thinner in response to demands of the industry based on increased usage of the packages in portable electronic devices and, in particular, the demand for increased memory capacity despite the continuing decrease in the size of such devices. Thus, use of separate redistribution elements such as interposers or a top die with a redistribution layer thereon in combination with a lead frame paddle presents significant obstacles to stacking more semiconductor dice in a package due to minimum die thickness requirements for adequate yield. For example, the specification thickness for a TSOP package envelope is 1 mm (1.2 mm with lead finger standoff), requiring unacceptably thin, extremely fragile dice on the order of 80 μm thick if a lead frame paddle is employed.